Description

Description

- Define and architect margin-to-fail validation strategies to uncover weaknesses and failure conditions in high-speed SerDes PHYs across multiple process, voltage, temperature, and different system environments - Develop and implement stress-to-fail methodologies, covering end-to-end systems, such as stressing equalization paths, clocking structures, jitter sensitivities, and link training edge cases, etc. - Collaborate early with SerDes design, architecture, and system teams to review specifications, define coverage priorities, and to build in needed design-for-test (DFT) insertion or sensors to improve observability, measurements, pattern generators, observability hooks, etc. - Lead hands-on lab experiments to validate assumptions, isolate issues, root-cause failures, and fine-tune test coverage for both standalone IP and system-level interactions - Partner with the validation team to balance test coverage and execution time, helping shape an efficient validation pipeline that enhances risk reduction within time constraints - Analyze silicon behaviors across multiple builds and revisions; derive insights to guide validation refinement and inform design updates - Provide post-silicon feedback that improves future architectural decisions, design margins, and validation methodology - Guide junior validation engineers, share debug techniques, and contribute to internal standard processes for SerDes validation

Minimum Qualifications

• BS and a minimum of 20 years relevant industry experience or equivalent
• 10+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug

Preferred Qualifications

• PhD in Electrical Engineering or related field with 15+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug
• Hands-on lab experience with lab instrumentations such as oscilloscopes, BERTs, protocol analyzers, etc, and
• measurement setups tailored for SerDes PHYs
• Deep understanding of high-speed serial link protocols (PCIe, USB, Ethernet, DisplayPort, etc.) and equalization techniques (such as CTLE, DFE, FFE etc)
• Strong foundation in analog/mixed-signal design principles and familiarity with signal integrity (SI) and power integrity (PI) impacts
• Skilled in programming (Python, C/C++, etc.) and data analysis tools for validation automation and correlation studies
• Proven track record to break down complex problems, isolate issues, and root-cause at the circuit, protocol, and system levels
• Demonstrated experience in design-for-validation, including fault injection, internal monitors, and behavioral hooks
• Experience validating multi-lane PHYs with adaptive EQ, clocking and CDR paths, and challenging compliance requirements in various real systems
• Familiarity with production and characterization flows, including margin-to-fail and stress testing techniques
• Ability to guide test coverage optimization to reduce execution time without sacrificing risk coverage
• Experience providing post-silicon insights that shaped future design changes
• Passion for deep debug and a "find the flaw" mentality, with an interest to explore the unexpected

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $212,000 and $386,300, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .