Description

Description

As a member of our STA CAD team, you will: • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure • Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation • Develop and maintain scripts and methods for timing analysis and power reduction • Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams • Analysis of timing paths to identify key issues, including post-silicon timing debug • Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems

Minimum Qualifications

• Minimum requirement of BS and 10 years of relevant industry experience.

Preferred Qualifications

• Expert power user of static timing analysis tools and flows
• Advanced programming skills with Python and Tcl or other high level programming languages
• Proven track record of development and deployment of complex CAD flows and automation
• Familiar with STA of large high-performance SoC designs in deep sub-micron technologies
• Deep understanding of noise, cross-talk, variation, margins, and timing models
• Knowledge of timing/SDC constraints, hands on experience in creation and validation of constraints
• Excellent communicator who can accurately assess and describe issues to management as well as follow solutions through to completion

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .