Description

Description

As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Generation of block and full chip timing constraints. Own timing sign-off to make sure timing requirements are met across all corners, modes, and conditions. Work closely with various multi-functional teams on resolving sophisticated timing issues for major building blocks of sophisticated SoCs. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications.

Responsibilities

• As an STA Engineer, the day-to-day work involves performing static timing analysis across multiple corners and modes using tools like Synopsys PrimeTime.
• The role includes maintaining and validating SDC constraints, collaborating closely with RTL, synthesis, and physical design teams to resolve timing issues.
• Own STA sign-off for block and chip level including custom timing checks.
• Develop automation scripts in Tcl or Python to streamline analysis and reporting, prepare sign-off quality constraints, and ensure the design meets all performance and reliability targets before tape-out.

Minimum Qualifications

• BS and 3+ years of relevant industry experience.
• Hands-on experience in ASIC timing constraints generation and timing closure.
• Good knowledge in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing.
• Good understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and BIST testing.
• Own STA sign-off for block and chip level including custom timing checks.
• Hands on experience in timing/SDC constraints generation and management.
• Knowledge of low-power techniques including clock gating, power gating and multi-voltage designs.
• Proficient in scripting languages (Tcl and Perl/Python).
• Strong communication skills are a pre-requisite as the candidate will collaborate with a lot of different groups (e.g. digital design, DFT, physical design, etc.).

Preferred Qualifications

• MS and 3+ years of relevant industry experience.
• Strong background in Constraint analysis and debug, using industry standard tools such as Synopsys CA (Constraint Analyzer).
• Understand and implement improving existing methodologies and flows. Experience in reducing the number of timing signoff corners by merging different timing modes is highly desired.
• Solid understanding of timing corners/modes, process variations and signal integrity related issues.

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $139,500 and $258,100, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .