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Apple
Beaverton, Oregon, United States
(on-site)
Posted
4 days ago
Apple
Beaverton, Oregon, United States
(on-site)
Job Function
Engineering
CPU Debug and Power Management Microarchitect/RTL Engineer
The insights provided are generated by AI and may contain inaccuracies. Please independently verify any critical information before relying on it.
CPU Debug and Power Management Microarchitect/RTL Engineer
The insights provided are generated by AI and may contain inaccuracies. Please independently verify any critical information before relying on it.
Description
DescriptionAs a CPU Debug and Power Management Microarchitect/RTL Engineer, you will own or contribute to the following: • RTL ownership of CPU debug, trace, power management, clock management, and timer logic - development, assessment, and refinement of RTL design to target power, performance, area and timing goals • Micro-architecture development and specification - Work with a cross-functional team of silicon and software experts to explore and define architectural features, develop micro-architectural details, and arrive at a detailed specification • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification • Performance exploration and correlation - explore high performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance • Design delivery - Aid in debug of issues at SoC level related to CPU power management, clock control, and debug features. Work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum Qualifications
- Minimum BS and 10+ years of relevant industry experience
- Experience with Verilog or VHDL
- Experience with simulators and waveform debugging tools
- Experience with logic design with timing and power implications
Preferred Qualifications
- Knowledge and understanding of microprocessor architecture
- Expertise in one or more of the following areas: multiple clock/power domains and power management strategies, hardware debug and trace capabilities, DFT strategies, interrupt controllers, memory subsystem queuing, scheduling - starvation and deadlock avoidance, fabric communication protocols and interconnects
- SRAM design basics
- Understanding of low power microarchitecture techniques
- Understanding of high-performance design techniques and trade-offs
- Experience in C or C++ programming
- Experience using an interpretive language such as Python or Perl
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
Job ID: 80810311

Apple
Cupertino
,
California
,
United States
We’re a diverse collective of thinkers and doers, continually reimagining what’s possible to help us all do what we love in new ways. The people who work here have reinvented entire industries with the Mac, iPhone, iPad, and Apple Watch, as well as with services, including Apple TV, the App Store, Apple Music, and Apple Pay. And the same innovation that goes into our products also applies to our practices — strengthening our commitment to leave the world better than we found it.
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