Description

Description

In this role, you will be responsible for the following: Performing concept studies and provide direction in terms of performance, gate count and power for various digital designs. Writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. Providing high-quality RTL description, including assertions, for the design. Formal tools and static checkers will be used to guarantee RTL quality. Supporting design verification to insure bug-free first silicon. Driving functional and code coverage as well as timing closure for your designs. Supporting silicon bring-up, performance and power characterization.

Minimum Qualifications

• BS degree in technical discipline with minimum 3 years of relevant experience.

Preferred Qualifications

• RTL design using Verilog or SystemVerilog, assertion writing
• Design of state machines, data paths, arbitration and clock domain crossing logic
• Logic synthesis, timing constraints
• Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
• Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
• Prior experience in DDR PHY design and mixed-signal environment is a plus

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