Description

Description

Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers. As a member of the layout team of the microprocessor group, you will be responsible to deliver PDV clean layout, including the following: - Designing complex custom layout for digital circuits in deep SubMicron CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers. - Running a complete set of layout design verification tools available on megacells completed. - Working with the circuit design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering specifications and expectations. - Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits.

Minimum Qualifications

• Bachelors degree in relevant field of study + 3 years of relevant experience.

Preferred Qualifications

• We are looking for applicants experience in custom layout design of deep SubMicron CMOS circuits.
• High level proficiency in layout floorplanning, standard cell planning and hierarchical layout assembly.
• Good understanding of issues with RC delay, electromigration, self heating and cross capacitance.
• Recognize failure prone layout structures, dedicatedly work with designers for the best approach to problems.
• Excellent communication skills and able to work with multi-functional teams.
• Great skills on interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
• Knowledge of MENTOR GRAPHICS or CADENCE layout tools
• Scripting skills in CSH, PERL or SKILL are considered a plus, but not required.
• Experience in layout automation is considered a plus, but not required.
• Experience in memory compiler development is considered a plus, but not required.
• Experience designing low noise, low power datapaths or Memory layout structures, etc.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .