Description

Description

In this role you will: - Work with the design team to review and enhance specifications. - Implement verification plans in coordination with design leads, verification leads and micro-architects. - Complete formal verification across multiple design blocks. - Conduct formal verification reviews with design and verification teams.

Minimum Qualifications

• BS degree in Computer Science, Computer Engineering, Electrical Engineering or equivalent field.
• Experience in programming/scripting languages.

Preferred Qualifications

• Knowledge of CPU or GPU design architectures, VLSI circuits, and digital logic design.
• Experience with HDLs such as Verilog/System Verilog and temporal logic assertion-based languages such as SVA.
• Exposure to formal verification and analysis of pipelined micro-architectures, MMUs, and cache coherency control mechanisms.
• Experience with formal tools, such as JasperGold, IFV, etc.
• Experience using academic formal verification tools.
• Understanding of abstraction techniques and formal verification technologies.
• Experience in reviewing and interpreting design specifications.
• Knowledge of constrained random verification methods.
• Ability to collaborate across teams.

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