Description

Description

Perform top-level verification for logic blocks in graphics processing unit (GPU) designs. Execute and provide status on test plan items. Port legacy test bench components in System Verilog and Universal Verification Methodology (UVM) including checkers and monitors. Develop top-level tests to validate chip level features. Enable and maintain regressions. Modify and maintain test benches and BFMs. Implement stimulus and analyze coverage. Debug simulation and silicon GPU failures. Work closely with design & micro-architecture teams to understand the functional goals of the design. Develop scripts for software engineering flows.

Minimum Qualifications

• BS required.
• Experience with Object Oriented Programming languages.
• Programming experience in C or C++.
• Experience with Verilog or other HDLs.

Preferred Qualifications

• Knowledge of GPU architectures.
• Understanding of CPU architectures.
• Familiarity with verification language such as System Verilog/UVM/OVM.
• Familiarity with various HDL simulators and waveform viewers like IES, VCS, DVE, Verdi.
• Understanding of constrained random verification process, functional/code coverage, and assertion methodology.
• Familiarity with Perl, Shell scripting, Makefiles, TCL.
• Prior exposure to code repositories like Perforce.
• Ability to work well on a team with a passion to learn from others.

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