Description

Description

Lead top-level verification teams for logic blocks in graphics processing unit (GPU) designs. Own overall development, execution, and tracking of team's test plans. Architect test bench methodology using Universal Verification Methodology (UVM) and System Verilog components. Build testing stimulus, coverage, and regression strategy. Own and maintain test benches and BFMs. Debug simulation and silicon GPU failures. Drive discussions with design & micro-architecture teams, as well as with other multi-functional teams to coordinate verification efforts. Generate and present weekly status to GPU leadership team.

Minimum Qualifications

• BS + 10 years relevant experience
• Background in CPU or GPU architectures.
• Experience working with Verilog or other HDLs.
• Background in architecting test benches with System Verilog and UVM/OVM.
• Experience with constrained random verification process, functional and code coverage, ad assertion methodology.
• Experience in debugging complex design and environmental issues.

Preferred Qualifications

• Ability to manage multiple priorities under strict schedule deadlines.
• Expertise in GPU architectures.
• Experience with various HDL simulators and waveform viewers like IES, VCS, DVE, Verdi.
• Experience with Perl, Shell scripting, Makefiles, TCL.
• Ability to work well on a team with experience in collaborating with teams across technical disciplines.

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