Description

Description

Perform top-level verification for logic blocks in graphics processing unit (GPU) designs. Write, execute, and track to test plans. Develop test bench components in System Verilog and Universal Verification Methodology (UVM) including checkers and monitors. Develop top-level tests to validate chip level features. Enable and maintain handle regressions. Write and maintain test benches and BFMs. Generate stimulus and implement/analyze coverage. Debug simulation and silicon GPU failures. Work closely with design & micro-architecture teams to understand the functional goals of the design. Collaborate with multi-functional teams to coordinate verification efforts across DV scopes. Develop scripts for software engineering flows.

Minimum Qualifications

• BS + 3 years of relevant experience.
• Background in CPU or GPU architectures.
• Experience working with Verilog or other HDLs.
• Experience with verification language such as System Verilog/UVM/OVM.
• Experience working with various HDL simulators and waveform viewers like IES, VCS, DVE, Verdi.

Preferred Qualifications

• Experience working with GPU architectures.
• Understanding of constrained random verification process, functional/code coverage, and assertion methodology.
• Ability to manage multiple priorities under strict schedule deadlines.
• Experience in developing test bench components in UVM including checkers and monitors.
• Familiarity with Perl, Shell scripting, Makefiles, TCL.
• Prior exposure to code repositories like Perforce.
• Ability to work well on a team with experience in collaborating with other teams.

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