Description

Description

As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block/chip level static timing constraints. Build full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration.

Minimum Qualifications

• Bachelors of Science in Electrical Engineering and 10 years experience preferred.

Preferred Qualifications

• The ideal candidate will have deep design experience in high PHY and/or SOC designs
• Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route
• Experience in developing and implementing Power-grid and Clock specifications
• Strong understanding of all aspects of Physical construction, Integration and Physical Verification
• Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design & Synthesis tools
• Deep Understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools
• Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level

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