Description

Description

In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits with embedded micro-controller, advanced DFT architectures and very low power design requirements. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing RTL assertions, debugging code, and otherwise interacting with the design verification team. Additionally, you will be responsible for various front end methodology flows that include pre-silicon power analysis, clock domain crossing, reset domain crossing and unified power flow UPF). You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.

Minimum Qualifications

• BS degree in technical discipline with minimum 10 years of relevant experience.

Preferred Qualifications

• Deep knowledge of mixed signal concepts
• Deep knowledge of RTL design fundamentals (control and data path).
• Deep knowledge of Verilog and SystemVerilog.
• Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers, reset domain crossing, unified power flow, logic equivalence checkers).
• Working knowledge of synthesis, static timing, and DFT (scan, analog/digital functional/production test).
• Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques.
• Deep knowledge of scripting languages. Perl and Python are plusses.
• Deep knowledge of Algorithm developments.
• Strong communication and presentation skills.
• SERDES architecture knowledge is a plus.

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