Description

Description

In this job you will get the opportunity to gain knowledge in designing micro-architecting digital blocks within sophisticated mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.

Minimum Qualifications

• BS degree in technical discipline with minimum 3 years of relevant experience

Preferred Qualifications

• Solid understanding of mixed signal concepts, RTL design, Verilog and SystemVerilog
• Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
• Validated knowledge of synthesis, static timing, DFT, is a plus
• Validated knowledge of SystemVerilog assertions, checkers, and other design verification techniques are a plus
• Knowledge of scripting languages. Perl and Python are plusses
• Strong communication and presentation skills

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .