Description

Description

In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.

Minimum Qualifications

• BS degree in technical discipline with minimum 10 years of relevant experience.

Preferred Qualifications

• Deep knowledge of mixed signal concepts
• Deep knowledge of RTL design fundamentals
• Deep knowledge of Verilog and System-Verilog
• Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
• Working knowledge of synthesis, static timing, DFT is a huge plus
• Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques
• Deep knowledge of scripting languages. Perl and Python are plusses
• Deep knowledge of Algorithm developments
• Strong communication and presentation skills SERDES knowledge is a plus

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .