Description

Description

We work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best in class power, performance, and area (PPA). We lead discussions with multi-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block-level specifications, mixed-signal implementations and behavioral modeling. We work closely with SOC teams to deliver IP views and ensure they meet the quality standards. While developing these complex IPs on regular basis, we interact with peers/management to communicate progress, discuss new ideas and drive new implementations/concepts making it an exciting and growth-oriented work environment.

Minimum Qualifications

• BSEE with 3+ years of proven experience.

Preferred Qualifications

• The ideal candidate should have deep understanding of AMS design with experience in high-speed serial links.
• Solid understanding of designing AMS circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
• Understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
• Deep understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops)
• Proven experience working on system and architecture teams to drive block-level and IP requirements
• Proven track record working with large teams and guiding junior engineers
• Experience with high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design concepts
• Experience and proven understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 20+ Gbps NRZ and PAM applications
• Experience with EQ adaptation methods and circuit interactions to improve PPA
• Solid understanding of CDR architectures and implementations
• Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS)
• Hands-on experience to drive lab testing, debug and data analysis
• Hands-on experience in advanced CMOS technologies, design with FinFet technology
• Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
• EXPERIENCE IN THE FOLLOWING AREAS IS A PLUS
• Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)
• Concepts of IP delivery and quality checks
• Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is helpful
• Skills in scripting and automation to improve efficiency are highly desirable

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .