Description

Description

In this highly transparent and interactive role, your primary responsibilities will include: - Reviewing Architecture and Design Specifications. - Extracting design features and developing attributes and verification plans. - Working with designers to verify DFT implementation and run various checks. - Implementing test benches, generating advised/constrained random tests. - Debugging failures, running gate level simulations, supervising bugs, and closing coverage. - Handling schedules and supporting multi-functional engineering effort. - Assisting in verification flows, automation scripts and regressions. - Working with test engineers to bring up test patterns on silicon.

Minimum Qualifications

• Bachelors Degree + 3 Years of Experience.

Preferred Qualifications

• Proven experience in large processors and/or SOC designs.
• Hands-on experience in directed or random verification, coverage analysis and assertions.
• Proficient in scripting languages such as Perl, Python or TCL
• Excellent skills in problem solving, communication and desire to seek new challenges.
• Good knowledge of general logic design, and exposure to DFT is a plus.

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