Description

Description

- Characterize parametric performance of High Speed IO PHYs (SERDES), PLLs, Sensors and other Custom HardIPs. - Define characterization plans, perform statistical data analysis, drive ATE-Bench correlation & data reviews across cross-functional teams and sign off on all silicon characterization activities. - Work with DFT and design teams to evaluate IP testability and drive new silicon debug. - Perform failure analysis to root-cause issues implement corrective actions and qualify cutting edge process technologies. - Work with Design, Validation, Test engineering, DFT, Program Management, and Manufacturing to support productization of next generation SoCs. - Complete yield and correlation analysis for all test insertions and support test time reduction related characterization activities.

Minimum Qualifications

• Bachelor's degree + 3 Years of Experience.

Preferred Qualifications

• Understanding of Test and characterization of High-Speed IO PHYs, PLLs, Sensors and related electrical specifications (eye diagrams, JTOL, signal integrity, de-embedding etc.), mixed-signal IPs.
• Experience working with Digital, Mixed Signal, SOC Devices and a solid understanding of ATE production testing. Hands on ATE and/or Bench experience is a plus.
• Statistical data analysis tools to perform high volume characterization & production data analysis.
• High Speed Digital and Analog circuits, Design for Test and Manufacturing Concepts.
• Experience in scripting (Python, PERL etc.) is a plus.

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