Description

Description

- Work with design teams to understand and debug constraints and facilitate logic changes to improve timing. - Work with the Physical Design team, highlighting issues and best practices. - Help create timing ECO's for project tapeout. - Create and maintain scripts and methodologies for analysis and runs. - Create documentation and help with guidelines/specs. - Deep analysis of timing paths to identify key issues. - Implement timing infrastructure.

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Strong programming skills with TCL.

Preferred Qualifications

• Experience with large design STA and/or Timing Closure.
• Experience with timing of large high-performance SoC designs in sub-micron technologies.
• Deep understanding of noise, crosstalk, OCV and other timing modeling effects.
• Knowledge of circuit modeling including timing models, worst-case timing corner selection, and SPICE simulation.
• Experience in ECO techniques and implementation.
• Experience with other scripting languages such as Perl or python.
• Good communicator who can accurately describe issues, propose solutions, and drive them through completion.

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