Description

Description

As a Power Flow Methodology Engineer, you'll deliver new automated solutions and capabilities for the Silicon Engineering Power team to build chips that are more power efficient than ever before. You will help with the architecture, implementation, and verification of new low-power design and verification flows and help to craft the low-power methodologies across a wide variety of future technologies. The work involves creating flows and tools related to power analysis, optimization and verification which may be run as part of RTL construction/verification, synthesis, or P&R. Additional responsibilities include communicating with the design team to answer questions about the materials and drive issues to resolution.

Minimum Qualifications

• A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience.

Preferred Qualifications

• Good understanding of VLSI designs and SOC design flows.
• Strong passion for scripting and applying low-power domain-specific knowledge to create new software solutions.
• Strong background with flow development and/or object-oriented language algorithm design such as Python / C++ / Java.
• Solid understanding and proven track record using modern software testing and development practices.
• Good written/verbal communications skills are required.
• Knowledge of Tcl / Perl, experience with EDA tools, GUI development, and/or low-power concepts such as UPF and low-power design is a plus.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .