Description

Description

As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications. Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs.

Minimum Qualifications

• Bachelors Degree + 3 Years of Experience.

Preferred Qualifications

• Strong fundamentals in the area of Digital design
• Self-starter and highly motivated
• Proficient in scripting languages (TCL and Perl)
• Familiarity with ASIC design timing concepts
• Exposure in STA tools (Primetime) is a plus
• Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks
• Familiarity in Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer) is desirable but not required
• Knowledge of timing corners/modes, process variations and signal integrity related issues is a plus
• Ability to commnicate optimally across all internal groups

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